Resume

General Information

Full Name Trung Canh Nguyen
Date of Birth 30th December 1990
Languages Vietnamese, English

Experience

  • 2022 - NOW
    Senior FPGA developer
    SoC.one, USA
    • Architecture AIO 5G testbed
    • FPGA development
      • Offloading L1 functions on Intel FPGA platform
      • Interfaces integration including eCPRI and PCIe
  • 2021-2022
    Senior Field Applications Engineer
    Avnet, Inc., Singapore
    • Demand creation and providing technical support to customer in South-East Asia, focusing on AMD-Xilinx product lines
    • Design and prototype AI vision application on Kria platform including Face Detection/ Recognition and ANPR.
    • Providing technical support and training to customers.
  • 2021
    Senior FPGA developer
    Techvico, Hanoi, Vietnam.
    • Co-operating with Pinnacle ISP (USA) for designing and prototyping ISP accelerators.
      • Implementing novel image processing algorithms on FPGA using Xilinx High Level Synthesis flow.
      • Building and prototyping a video streaming system which uses Techvico’s accelerators and Xilinx DPU as overlay. The system runs on Kria Starter Kit.
  • 2020 - 2021
    FPGA developer
    Vinsmart, Vingroup Corp. , Hanoi, Vietnam
    • 5G-RRU
      • Developed 2 RRU vesions based on ADRV9025 and ADRV9009
      • Completed Macrocell 8T8R with peak throughput 800 Mbps
    • 5G-L1
      • Lead a team of 3 engineers to develop PDSCH bit-processing (@300MHz). Total processing latency < 150 us (TBS max = 1.2 Megabits)
  • 2017 - 2020
    FPGA developer
    Viettel High Technology Industries Corporation, Hanoi, Vietnam
    • 5G-L1
      • Lead a team of 5 engineers to design and implement L1 data channel PUSCH and control channel (PUCCH format 3) on Xilinx FPGA.
    • Radio design
      • Completed DFE implementation for 2T2R (support DPD, CFR, DUC operations - ACLR = 50 dbm, satisfying 3GPP requirement)
  • 2016 - 2017
    Research assistant
    Microelectronics systems design research group, TU Kaiserslautern, Kaiserslautern, Germany
    • Designed and prototyped an FPGA-based accelerator for computing intraday financial correlation (the most time-consuming part of Risk Assesment process). Achieved a throughput of 1.087 cycle/floating point number and a 68x speedup in runtime (FPGA@100MHz)

Education

  • 2014-2017
    Master of Science
    TU Kaiserslautern, Kaiserslautern, Germany
    • Specilization | Embedded System
    • Grade | 1.5 (∼ 92%)
  • 2008-2013
    Bachelor of Engineer
    Hanoi University of Science and Technology (HUST), Hanoi, Vietnam
    • Specilization | Electrical and Electronics Engineering
    • Grade | 8.64 out of 10

Other Interests